FBSL=00, LPUARTSRC=00, TRACECLKSEL=0, PLLFLLSEL=00, CLKOUTSEL=000
System Options Register 2
| CLKOUTSEL | CLKOUT select 0 (000): FlexBus CLKOUT 2 (010): Flash clock 3 (011): LPO clock (1 kHz) 4 (100): MCGIRCLK 6 (110): OSCERCLK0 7 (111): IRC 48 MHz clock |
| FBSL | FlexBus security level 0 (00): All off-chip accesses (instruction and data) via the FlexBus are disallowed. 1 (01): All off-chip accesses (instruction and data) via the FlexBus are disallowed. 2 (10): Off-chip instruction accesses are disallowed. Data accesses are allowed. 3 (11): Off-chip instruction accesses and data accesses are allowed. |
| TRACECLKSEL | Debug trace clock select 0 (0): MCGOUTCLK 1 (1): Core/system clock |
| PLLFLLSEL | PLL/FLL clock select 0 (00): MCGFLLCLK clock 1 (01): MCGPLLCLK clock 3 (11): IRC48 MHz clock |
| LPUARTSRC | LPUART clock source select 0 (00): Clock disabled 1 (01): MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL]. 2 (10): OSCERCLK clock 3 (11): MCGIRCLK clock |